ANALYSE NUMERIQUE MULTI- ECHELLE DE LA DEFORMATION D'UN EMPILEMENT DE COUCHE MINCE DESTINE A DES APPLICATION MICRO ELECTRONIQUE

Abstract

The manufacturing of microelectronic components is moving towards increased miniaturization and optimized performance to meet economic and strategic challenges. To achieve these objectives, manufacturers use thin films of various materials, typically deposited on silicon substrates. However, these manufacturing methods, carried out at different temperatures, cause warping due to differences in the coefficients of thermal expansion between the thin layers making up the stack. This warping can disrupt the manufacturing process, leading to issues such as defects during photolithography, difficulties in automated equipment detecting wafers, or even risks of breakage during handling. To avoid these complications, it is essential to predict the level and distribution of deformations within the stack. Numerical simulation is commonly used to study these problems, offering significant advantages for rapid industrial application. The work conducted within the framework of this thesis is based on three main points: 1. Numerically determine the warping of the Si/USG/Pt stack while respecting the steps of the manufacturing process. 2. Introduce and validate simplifications to facilitate numerical modeling, notably replacing the actual thermal loading with an equivalent loading and integrating homogenization techniques to obtain an equivalent model. 3. Numerically study the effect of trimming on reducing the warping of a thin-film stack. The numerical approaches undertaken in this work were validated by comparisons with experimental results. The results thus obtained highlight the importance of taking warping into account in layer stacks. The contribution to simplifying the numerical approach can be used by industry professionals to reduce the time allocated to developing new microelectronic solutions.